The present invention relates generally to electronic packaging technology and, more particularly, to electronic packaging technology applicable to power semiconductor devices.
Advanced semiconductor device technologies, such as, Integrated Gate Bipolar Transistor (IGBT), Metal Oxide Semiconductor Field effect Transistor (MOSFET), MOS Controlled Thyristor (MCT) offer improve thermal and electrical performance for a broad range of applications in a wide range of power levels. However, to fully utilize the capabilities of such devices there is a need to provide improved packaging designs.
Typical semiconductor module designs employ wire bonds for connecting semiconductor devices to power busses and control terminals. The semiconductor devices are commonly soldered onto a metalized insulating ceramic substrate and subsequently bonded to a heat spreader. Typically, an injection molded polymer shell covers the module, exposing only the input/output and control terminals and the heat spreader. The heat spreader is attached to a heat sink and thermal contact between the heat spreader and the heat sink is achieved through a thermal paste or a thermally conductive polymer. Disadvantages of wire-bond based semiconductor module designs include relatively high parasitic impedance, high volume and weight, high thermal resistance, and limited reliability primarily due to the wire bonds.
Power overlay (POL) technology eliminates use of wire bonds and offers significant advantages over the wire-bond based packaging of power modules, for example, higher packaging density, lower package parisitics, enhanced reliability, lower weight, smaller size, and higher efficiency. A typical power overlay fabrication process involves use of a dielectric film stretched on a frame. An adhesive layer is applied to the dielectric film, on which vias are formed by laser ablation, followed by attachment of the semiconductor devices to the dielectric film. This is followed by metallization and formation of circuits on the film by electroplating a thick layer of copper on the dielectric film and into the vias. The resulting package is then attached to a substrate. In some instances, “feed-through” structures or “shims”, which are used to connect the metalized layer with the substrate electrically may be separately attached to the dielectric film. Accordingly, in POL technology, power and control circuits to devices are achieved through the metalized vias, thus obviating the need for bond wires.
However, the current POL fabrication process may still pose economic and technical challenges because of the number of steps and the time involved for each step. For example, the metallization step typically involves electroplating for hours to achieve the desired copper thickness for current handling, which significantly increases the cost of the POL process. Further, the use of a frame reduces the available area for packaging and also adds processing steps to the POL fabrication process. The use of separate copper shims may further increase the cost of the fabrication step and may pose technical challenges, such as, lower adhesion.
Thus, there is a need to streamline POL fabrication processes in order to provide cost-effective semiconductor device packaging fabrication processes that overcome one or more disadvantages associated with current POL processes.